Separate pipeline registers, hazard detection (data forwarding), branch prediction. 3. Memory Controllers & Arbitration Example: AHB-Lite Slave (Burst Write) module ahb_slave ( input HCLK, HRESETn, input HTRANS, HWRITE, HREADY, input [31:0] HADDR, HWDATA, output reg HREADYOUT, HRESP, output reg [31:0] HRDATA ); reg [31:0] memory [0:1023];
// Stage 2: Decode & Register Read (combinational) wire [4:0] rs1 = IF_ID_instr[19:15]; wire [4:0] rs2 = IF_ID_instr[24:20]; wire [31:0] reg_data1 = regfile[rs1]; wire [31:0] reg_data2 = regfile[rs2];
// Stage 3: Execute (ALU) always @(posedge clk) begin ID_EX_instr <= IF_ID_instr; ID_EX_pc <= IF_ID_pc; ID_EX_rs1 <= reg_data1; ID_EX_rs2 <= reg_data2; end Advanced Chip Design- Practical Examples In Verilog
wire [3:0] wgray = wptr ^ (wptr >> 1); wire [3:0] rgray = rptr ^ (rptr >> 1);
Gray code pointers, full/empty detection, metastability hardening. 5. Low-Power Design Techniques Clock Gating (Integrated with synthesis) module clock_gated_reg ( input clk, en, d, output reg q ); wire gated_clk; assign gated_clk = clk & en; // NOT for FPGA (glitchy) // Better: use latch-based AND gate reg en_latch; always @(clk or en) if (!clk) en_latch = en; assign gated_clk = clk & en_latch; output reg q )
always @(posedge clk_dst or negedge rst_n) begin if (!rst_n) sync, meta <= 2'b00; else sync, meta <= meta, sig_src; end
always @(posedge HCLK or negedge HRESETn) begin if (!HRESETn) HREADYOUT <= 1'b1; else begin if (HREADY && HTRANS == NONSEQ) begin if (HWRITE) memory[HADDR[11:2]] <= HWDATA; else HRDATA <= memory[HADDR[11:2]]; HREADYOUT <= 1'b1; end else HREADYOUT <= 1'b1; // wait-state insertion possible end end endmodule assign gated_clk = clk & en
// Stage 1: Instruction Fetch always @(posedge clk or negedge rst_n) begin if (!rst_n) begin pc <= 32'b0; IF_ID_instr <= 32'b0; end else begin pc <= pc_next; IF_ID_instr <= instr_mem_data; IF_ID_pc <= pc; end end